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HA-4900, HA-4902, HA-4905
Data Sheet September 1998 File Number 2855.3
Precision Quad Comparators
The HA-4900 series are monolithic, quad, precision comparators offering fast response time, low offset voltage, low offset current and virtually no channel-to-channel crosstalk for applications requiring accurate, high speed, signal level detection. These comparators can sense signals at ground level while being operated from either a single +5V supply (digital systems) or from dual supplies (analog networks) up to 15V. The HA-4900 series contains a unique current driven output stage which can be connected to logic system supplies (VLOGIC+ and VLOGIC-) to make the output levels directly compatible (no external components needed) with any standard logic or special system logic levels. In combination analog/digital systems, the design employed in the HA-4900 series input and output stages prevents troublesome ground coupling of signals between analog and digital portions of the system. These comparators' combination of features make them ideal components for signal detection and processing in data acquisition systems, test equipment and microprocessor/analog signal interface networks. For military grade product, refer to the HA-4902/883 data sheet.
Features
* Fast Response Time . . . . . . . . . . . . . . . . . . . . . . . . 130ns * Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0mV * Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . .10nA * Single or Dual Voltage Supply Operation * Selectable Output Logic Levels * Active Pull-Up/Pull-Down Output Circuit. No External Resistors Required
Applications
* Threshold Detector * Zero Crossing Detector * Window Detector * Analog Interfaces for Microprocessors * High Stability Oscillators * Logic System Interfaces
Ordering Information
PART NUMBER HA1-4900-2 TEMP RANGE (oC) -55 to 125 -55 to 125 0 to 75 0 to 75 0 to 75 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC PKG. NO. F16.3 F16.3 F16.3 E16.3 M16.3
Pinout
HA-4900, HA-4902 (CERDIP) HA-4905 (PDIP, CERDIP, SOIC) TOP VIEW
V L+ OUT 1 -IN 1 +IN 1 V+IN 2 -IN 2 OUT 2 1 2 4 3 4 5 3 6 7 8 + 16 OUT 4
HA1-4902-2 HA1-4905-5 HA3-4905-5 HA9P4905-5
+
15 -IN 4 14 +IN 4 13 V+
+
1 12 +IN 3 11 -IN 3 10 OUT 3 9 V L-
+
-
-2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
HA-4900, HA-4902, HA-4905
Absolute Maximum Ratings
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 33V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Voltage Between VLOGIC+ and VLOGIC-. . . . . . . . . . . . . . . . . . .18V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Power Dissipation (Notes 1, 2)
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 85 25 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 100 N/A Maximum Junction Temperature (Ceramic Package) . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HA-4900-2, HA-4902-2. . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-4905-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Die Characteristics
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VNumber of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Die Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mils x 105 mils
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175oC for ceramic packages, and below 150oC for plastic packages. 2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and VLOGIC shown in curves of Power Dissipation vs Supply Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For instance, the combination of +15V, -15V, +5V, 0V (V+, V-, VLOGIC+, VLOGIC-) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V, 0V gives a T.P.D. of 450mW. 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VSUPPLY = 15V VLOGIC+ = 5V, VLOGIC- = GND , HA-4900-2 -55oC to 125oC MIN TYP MAX HA-4902-2 -55oC to 125oC MIN TYP MAX MIN HA-4905-5 0oC to 75oC TYP MAX UNITS
PARAMETER INPUT CHARACTERISTICS Offset Voltage (Note 4)
TEMP (oC)
25 Full
V-
2 10 50 250
3 4 25 35 75 150 VIO + 0.3 VIO + 0.4 (V+) 2.4 -
V-
2 10 50 250
5 8 35 45 150 200 VIO + 0.5 VIO + 0.6 (V+) 2.6 -
V-
4 25 100 250
7.5 10 50 70 150 300 VIO + 0.5 VIO + 0.7 (V+) 2.4 -
mV mV nA nA nA nA mV mV V M
Offset Current
25 Full
Bias Current (Note 5)
25 Full
Input Sensitivity (Note 6)
25 Full
Common Mode Range Differential Input Resistance TRANSFER CHARACTERISTICS Large Signal Voltage Gain Response Time (tPD(0)) (Note 7) Response Time (tPD(1)) (Note 7)
Full 25
25 25 25
-
400 130 180
200 215
-
400 130 180
200 215
-
400 130 180
200 215
kV/V ns ns
2
HA-4900, HA-4902, HA-4905
Electrical Specifications
VSUPPLY = 15V VLOGIC+ = 5V, VLOGIC- = GND (Continued) , HA-4900-2 -55oC to 125oC MIN TYP MAX HA-4902-2 -55oC to 125oC MIN TYP MAX MIN HA-4905-5 0oC to 75oC TYP MAX UNITS
PARAMETER OUTPUT CHARACTERISTICS Output Voltage Level Logic "Low State" (VOL) (Note 8) Logic "High State" (VOH) (Note 8) Output Current ISINK ISOURCE
TEMP (oC)
Full Full
3.5
0.2 4.2
0.4 -
3.5
0.2 4.2
0.4 -
3.5
0.2 4.2
0.4 -
V V
Full Full
3.0 3.0
-
-
3.0 3.0
-
-
3.0 3.0
-
-
mA mA
POWER SUPPLY CHARACTERISTICS Supply Current, IPS (+) Supply Current, IPS (-) Supply Current, IPS (Logic) Supply Voltage Range VLOGIC+ (Note 2) VLOGIC- (Note 2) NOTES: 4. Minimum differential input voltage required to ensure a defined output state. 5. Input bias currents are essentially constant with differential input voltages up to 9V. With differential input voltages from 9V to 15V, bias current on the more negative input can rise to approximately 500A. This will also cause higher supply currents. 6. VCM = 0V. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This parameter includes the effects of offset voltage and voltage gain. 7. For tPD(1); 100mV input step, -10mV overdrive. For tPD(0); -100mV input step, 10mV overdrive. Frequency 100Hz; Duty Cycle 50%; Inverting input driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V. 8. For VOH and VOL: ISINK = ISOURCE = 3.0mA. For other values of VLOGIC; VOH (Min) = VLOGIC + -1.5V. Full Full 0 -15.0 +15.0 0 0 -15.0 +15.0 0 0 -15.0 +15.0 0 V V 25 25 25 6.5 4 3.5 20 8 4 6.5 4 3.5 20 8 4 7 5 3.5 20 8 4 mA mA mA
Test Circuit and Waveform
+15V +5V OVERDRIVE tPD(0) tPD(1)
DUT + INPUT VOUT 100mV VTH = 0V 100mV VTH = 0V OVERDRIVE
-15V
OUTPUT 1.5V 1.5V tPD(1) tPD(0) t=0 t=0
FIGURE 1.
3
HA-4900, HA-4902, HA-4905 Schematic Diagram
R1 500 PR1 200k Q1 Q3 D4B D4A Q4 Q4C D45 Q7 Q19 Q5 R16 540 +IN BIAS 1 Q18 Q17 Q21 Q22 D35 -IN Q33 Q34 Q30 Q20 Q36 D39 Q37 Q38 Q28 R9 4k R10 4k Q2 Q11 R2 13k Q12 D11A R3 1k Q13 R6 2.5k R4 1k Q14 R7 2.5k R5 360 Q15 Q16 Q26 Q23 Q24 Q25 R11 8k R12 Q29A 8k Q29 D29B R24 14k R15 8k Q10 R20D 1k R20C 1k R20B 1k R20A 1k R21 1k MN1 MN3 MN2 R17 19k R14 5k R23 MN5 100 Q31 R22 100 Q32 OUT MN6 VLOGIC+ V+ R18 664
BIAS 2 Q9D
BIAS 3 BIAS 4 D9A Q9B Q9A Q9C
VLOGICMN4 V-
ONE FOURTH ONLY
Applying the HA-4900 Series Comparators
Supply Connections
This device is exceptionally versatile in working with most available power supplies. The voltage applied to the V+ and Vterminals determines the allowable input signal range; while the voltage applied to the VL+ and VL- determines the output swing. In systems where dual analog supplies are available, these would be connected to V+ and V-, while the logic supply and return would be connected to VLOGIC+ and VLOGIC -. The analog and logic supply commons can be connected together at one point in the system, since the comparator is immune to noise on the logic supply ground. A negative output swing may be obtained by connecting VL+ to ground and VL- to a negative supply. Bipolar output swings (15VP-P, Max) may be obtained using dual supplies. In systems where only a single logic supply is available (+5V to 15V), V+ and VLOGIC+ may be connected together to the positive supply while V- and VLOGIC- are grounded. If an input signal could swing negative with respect the V- terminal, a resistor should be connected in series with the input to limit input current to < 5mA since the C-B junction of the input transistor would be forward biased.
Power Supply Decoupling
Decouple all power supply lines with 0.01F ceramic capacitors to ground line located near the package to reduce coupling between channels or from external sources.
Response Time
Fast rise time (<200ns) input pulses of several volts amplitude may result in delay times somewhat longer than those illustrated for 100mV steps. Operating speed is optimized by limiting the maximum differential input voltage applied, with resistor-diode clamping networks.
Typical Applications
Data Acquisition System
In this circuit the HA-4900 series is used in conjunction with a D to A converter to form a simple, versatile, multi-channel analog input for a data acquisition system. In operation the processor first sends an address to the D to A, then the processor reads the digital word generated by the comparator outputs. To perform a simple comparison, the processor sets the D to A to a given reference level, then examines one or more comparator outputs to determine if their inputs are above or below the reference. A window comparison consists of two such cycles with 2 reference levels set by the D to A. One way to digitize the inputs would be for the processor to increment the D to A in steps. The D to A address, as each comparator switches, is the digitized level of the input. While stairstepping the D to A is slower than successive approximation, all channels are digitized during one staircase ramp.
Unused Inputs
Inputs of unused comparator sections should be tied to a differential voltage source to prevent output "chatter."
Crosstalk
Simultaneous high frequency operation of all other channels in the package will not affect the output logic state of a given channel, provided that its differential input voltage is sufficient to define a given logic state (VIN VOS). Low level or high impedance input lines should be shielded from other signal sources to reduce crosstalk and interference.
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HA-4900, HA-4902, HA-4905
Window Detector
LATCH D/A MEMORY INTERFACE
ANALOG INPUTS
INTERFACE
The high switching speed, low offset current and low offset voltage of the HA-4900 series makes this window detector circuit extremely well suited to applications requiring fast, accurate, decision-making. The circuit above is ideal for industrial process system feedback controllers or "out-oflimit" alarm indicators.
+15V V L+
MICROPROCESSOR COMPARATORS ANALOG INPUT MODULE PROCESSOR
INPUT
+ HIGH
HIGH REF
-
+5.0V
Logic Level Translators
The HA-4900 series comparators can be used as versatile logic interface devices as shown in the circuits above. Negative logic devices may also be interfaced with appropriate supply connections. If separate supplies are used for V- and VLOGIC-, these logic level translators will tolerate several volts of ground line differential noise.
+5.0V +5V TO +15V V L+ 4.7k + 1/4 HA-4900 10k + 1/4 HA-4900 +5.0V V+ 1/2 HA-4900 -15V
IN WINDOW 1/4 HD-74C02
LOW REF
+ LOW
-
Oscillator/Clock Generator
This self-starting fixed frequency oscillator circuit gives excellent frequency stability. R1 and C1 comprise the frequency determining network while R2 provides the regenerative feedback. Diode D1 enhances the stability by compensating for the difference between VOH and VSUPPLY. In applications where a precision clock generator up to 100kHz is required, such as in automatic test equipment, C1 may be replaced by a crystal.
V+ R2 150k D1 V+
1N914s 10k
-
+ 1/4 HA-4900
+ 1/4 HA-4900
TTL TO CMOS
-
CMOS TO TTL
1N914 150k
RS-232 To CMOS Line Receiver
This RS-232 type line receiver to drive CMOS logic uses a Schmitt trigger feedback network to give about 1V input hysteresis for added noise immunity. A possible problem in an interface which connects two equipments, each plugged into a different AC receptacle, is that the power line voltage may appear at the receiver input when the interface connection is made or broken. The two diodes and a 3W input resistor will protect the inputs under these conditions.
+10V 4.7k 3W
150k
+ 1/4 HA-4900
-
1 f ----------------------2.1R 1 C 1
C1
R1 50k
Schmitt Trigger (Zero Crossing Detector With Hysteresis)
1/4 HA-4900 + 1N4001s 1k 56k 51k
1k
This circuit has a 100mV hysteresis which can be used in applications where very fast transition times are required at the output even though the signal input is very slow. The hysteresis loop also reduces false triggering due to noise on the input. The waveforms below show the trip points developed by the hysteresis loop.
5
HA-4900, HA-4902, HA-4905
+15V +5V VOH VOH 4.2V R2 2k 0V R1 100 R3 13k -15V VTRIPVTRIP+
1/4 HA-4900 + -15V
INPUT TO OUTPUT WAVEFORM SHOWING HYSTERESIS TRIP POINTS
Typical Performance Curves
100
TA = 25oC, VS = 15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified
INPUT BIAS CURRENT (nA)
60
INPUT OFFSET CURRENT (nA)
80
15
10
40
5
20
0 -55 -25 0 25 50 75 100 125 TEMPERATURE (oC)
0 -55 -25 0 25 50 75 100 125 TEMPERATURE (oC)
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE
80
INPUT BIAS CURRENT (nA)
60
40
20
0 -15
-12
-9
-6
-3
0
+3
+6
+9
+12
+15
COMMON MODE INPUT VOLTAGE
FIGURE 4. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE (VDIFF = 0V)
6
HA-4900, HA-4902, HA-4905 Typical Performance Curves
12 10 SUPPLY CURRENT (mA) 8 6 4 IPSL, VOUT = L 2 IPSL, VOUT = H 0 -50 -25 0 25 50 75 100 125 TEMPERATURE (oC) 1 0 -50 -25 0 25 50 TEMPERATURE (oC) 75 100 125 VS = 15V VLOGIC+ = 5V VLOGIC- = GND
TA = 25oC, VS = 15V, VLOGIC+ = 5V, VLOGIC- = 0V, Unless Otherwise Specified (Continued)
7 IPSL, VOUT = H SUPPLY CURRENT (mA) IPS+, VOUT = L 6 5 IPS+, VOUT = H 4 IPS+, VOUT = L 3 2 V+ = 5V, V- = GND VLOGIC+ = 5V VLOGIC- = GND IPSL, VOUT = L
IPS+, VOUT = H IPS-, VOUT = L
IPS-, VOUT = H
FIGURE 5. SUPPLY CURRENT vs TEMPERATURE (FOR 15V SUPPLIES AND +5V LOGIC SUPPLY)
FIGURE 6. SUPPLY CURRENT vs TEMPERATURE (FOR SINGLE +5V OPERATION)
5 4 VOUT (V) 3 2 1 0 0 VIN OVERDRIVE = 20mV OVERDRIVE = 5mV OVERDRIVE = 2mV VOUT (V)
5 4 OVERDRIVE = 20mV 3 2 1 0 +100mV VIN OVERDRIVE = 2mV OVERDRIVE = 5mV
-100mV 0 100 200 TIME (ns) 300 400
0 0 100 200 TIME (ns) 300 400
FIGURE 7. RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES
2.0 1.75 PACKAGE DISSIPATION (W) 1.50 1.25 1.0 0.75 0.50 SOIC 0.25 0 0 25 50 75 100 125 TEMPERATURE (oC) PDIP POWER DISSIPATION (mW) CERDIP
250
200
150
V+
100
V-
50 VLOGIC+ 0 0 2 4 6 8 10 SUPPLY VOLTAGE (V) 12 14
FIGURE 8. MAXIMUM PACKAGE DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 9. POWER DISSIPATION vs SUPPLY VOLTAGE (NO LOAD CONDITION)
7
HA-4900, HA-4902, HA-4905
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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